diff -urN kernel26/arch/arm/mach-pxa/h4000/h4000.c kernel26_b/arch/arm/mach-pxa/h4000/h4000.c --- kernel26/arch/arm/mach-pxa/h4000/h4000.c 2006-05-29 17:30:51.000000000 -0600 +++ kernel26_b/arch/arm/mach-pxa/h4000/h4000.c 2006-06-04 14:12:44.000000000 -0600 @@ -48,6 +48,31 @@ void h4000_ll_pm_init(void); +static struct resource h4000_mmc_resources[] = { + [0] = { // control regs + .start = PXA_CS4_PHYS+0x1000, + .end = PXA_CS4_PHYS+0x1400, + .flags = IORESOURCE_MEM, + }, + [1] = { // config regs + .start = PXA_CS4_PHYS+0x400, + .end = PXA_CS4_PHYS+0x600, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = IRQ_GPIO(GPIO_NR_H4000_SD_IRQ_N), + .end = IRQ_GPIO(GPIO_NR_H4000_SD_IRQ_N), + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device h4000_mmc = { + .name = "asic3_mmc", + .num_resources = ARRAY_SIZE(h4000_mmc_resources), + .resource = h4000_mmc_resources, + .dev = { .platform_data = &h4000_asic3.dev}, +}; + static struct platform_device h4000_lcd = { .name = "h4000_lcd", }; static struct platform_device h4300_kbd = { .name = "h4300_kbd", }; static struct platform_device h4000_buttons = { .name = "h4000_buttons", }; @@ -62,6 +87,7 @@ &h4000_ts, &h4000_udc, &h4000_pcmcia, + &h4000_mmc, }; static struct asic3_platform_data h4000_asic3_platform_data = { @@ -97,6 +123,7 @@ .alt_function = 0x0000, .sleep_conf = 0x000c, }, + .bus_shift = 0, .child_platform_devs = h4000_asic3_devices, .num_child_platform_devs = ARRAY_SIZE(h4000_asic3_devices), }; @@ -122,7 +149,6 @@ }; EXPORT_SYMBOL(h4000_asic3); - void h4000_set_led(int color, int duty_time, int cycle_time) { if (color == H4000_RED_LED) { diff -urN kernel26/drivers/mmc/asic3_mmc.c kernel26_b/drivers/mmc/asic3_mmc.c --- kernel26/drivers/mmc/asic3_mmc.c 2006-06-04 13:39:01.000000000 -0600 +++ kernel26_b/drivers/mmc/asic3_mmc.c 2006-06-04 14:07:49.000000000 -0600 @@ -47,6 +47,7 @@ #include #include #include +#include #include #include @@ -54,206 +55,6 @@ #include #include -#include -#include - -/***************************************************************************** - * The SD configuration registers are at a completely different location - * in memory. They are divided into three sets of registers: - * - * SD_CONFIG Core configuration register - * SD_CTRL Control registers for SD operations - * SDIO_CTRL Control registers for SDIO operations - * - *****************************************************************************/ - -#define HX4700_ASIC3_SD_CONFIG(_b, s,x) \ - (\ - (*((volatile s *) ((_b) + _HX4700_ASIC3_SD_CONFIG_Base + (_HX4700_ASIC3_SD_CONFIG_ ## x))))) - -#define _HX4700_ASIC3_SD_CONFIG_Base 0x0200 - -#define _HX4700_ASIC3_SD_CONFIG_Command 0x04 /* R/W: Command */ -#define _HX4700_ASIC3_SD_CONFIG_Addr0 0x10 /* [9:31] SD Control Register Base Address */ -#define _HX4700_ASIC3_SD_CONFIG_Addr1 0x12 /* [9:31] SD Control Register Base Address */ -#define _HX4700_ASIC3_SD_CONFIG_IntPin 0x3c /* R/O: interrupt assigned to pin */ -#define _HX4700_ASIC3_SD_CONFIG_ClkStop 0x40 /* Set to 0x1f to clock SD controller, 0 otherwise */ -#define _HX4700_ASIC3_SD_CONFIG_ClockMode 0x42 /* Control clock of SD controller */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_PinStatus 0x44 /* R/0: read status of SD pins */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_Power1 0x48 /* Power2 is at 0x49 */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_Power3 0x4a /* */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_CardDetect 0x4c /* */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_Slot 0x50 /* R/O: define support slot number */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0xF0 /* Could be used for gated clock (don't use) */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0xF1 /* Could be used for gated clock (don't use) */ -#define _HX4700_ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0xF8 /* Bit 1: double buffer/single buffer */ - -#define HX4700_ASIC3_SD_CONFIG_Command(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, Command ) -#define HX4700_ASIC3_SD_CONFIG_Addr0(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, Addr0 ) -#define HX4700_ASIC3_SD_CONFIG_Addr1(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, Addr1 ) -#define HX4700_ASIC3_SD_CONFIG_IntPin(_b) HX4700_ASIC3_SD_CONFIG(_b, u8, IntPin ) -#define HX4700_ASIC3_SD_CONFIG_ClkStop(_b) HX4700_ASIC3_SD_CONFIG(_b, u8, ClkStop ) -#define HX4700_ASIC3_SD_CONFIG_ClockMode(_b) HX4700_ASIC3_SD_CONFIG(_b, u8, ClockMode ) -#define HX4700_ASIC3_SD_CONFIG_SDHC_PinStatus(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, SDHC_PinStatus ) -#define HX4700_ASIC3_SD_CONFIG_SDHC_Power1(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, SDHC_Power1 ) -#define HX4700_ASIC3_SD_CONFIG_SDHC_Power3(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, SDHC_Power3 ) -#define HX4700_ASIC3_SD_CONFIG_SDHC_CardDetect(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, SDHC_CardDetect ) -#define HX4700_ASIC3_SD_CONFIG_SDHC_Slot(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, SDHC_Slot ) -#define HX4700_ASIC3_SD_CONFIG_SDHC_ExtGateClk1(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, SDHC_ExtGateClk1 ) -#define HX4700_ASIC3_SD_CONFIG_SDHC_ExtGateClk3(_b) HX4700_ASIC3_SD_CONFIG(_b, u16, SDHC_ExtGateClk3 ) - -#define CLOCK_MODE_DIV_CLOCK_ENABLE (0 << 0) -#define CLOCK_MODE_DIV_CLOCK_DISABLE (1 << 0) -#define SD_CONFIG_CLKSTOP_ENABLE_ALL 0x1f - - -#define _HX4700_ASIC3_SD_CTRL_Base 0x0800 - -#define HX4700_ASIC3_SD(_b, s,x) \ - (\ - (*((volatile s *) ((_b) + _HX4700_ASIC3_SD_CTRL_Base + (_HX4700_ASIC3_SD_CTRL_ ## x))))) - -#define _HX4700_ASIC3_SD_CTRL_Cmd 0x00 /* RW */ -#define _HX4700_ASIC3_SD_CTRL_Arg0 0x04 -#define _HX4700_ASIC3_SD_CTRL_Arg1 0x06 -#define _HX4700_ASIC3_SD_CTRL_StopInternal 0x08 -#define _HX4700_ASIC3_SD_CTRL_TransferSectorCount 0x0a -#define _HX4700_ASIC3_SD_CTRL_Response0 0x0c -#define _HX4700_ASIC3_SD_CTRL_Response1 0x0e -#define _HX4700_ASIC3_SD_CTRL_Response2 0x10 -#define _HX4700_ASIC3_SD_CTRL_Response3 0x12 -#define _HX4700_ASIC3_SD_CTRL_Response4 0x14 -#define _HX4700_ASIC3_SD_CTRL_Response5 0x16 -#define _HX4700_ASIC3_SD_CTRL_Response6 0x18 -#define _HX4700_ASIC3_SD_CTRL_Response7 0x1a -#define _HX4700_ASIC3_SD_CTRL_CardStatus 0x1c -#define _HX4700_ASIC3_SD_CTRL_BufferCtrl 0x1e -#define _HX4700_ASIC3_SD_CTRL_IntMask0 0x20 -#define _HX4700_ASIC3_SD_CTRL_IntMask1 0x22 -#define _HX4700_ASIC3_SD_CTRL_CardClockCtrl 0x24 -#define _HX4700_ASIC3_SD_CTRL_MemCardXferDataLen 0x26 -#define _HX4700_ASIC3_SD_CTRL_MemCardOptionSetup 0x28 -#define _HX4700_ASIC3_SD_CTRL_ErrorStatus0 0x2c -#define _HX4700_ASIC3_SD_CTRL_ErrorStatus1 0x2e -#define _HX4700_ASIC3_SD_CTRL_DataPort 0x30 -#define _HX4700_ASIC3_SD_CTRL_TransactionCtrl 0x34 -#define _HX4700_ASIC3_SD_CTRL_SoftwareReset 0xe0 - -#define HX4700_ASIC3_SD_CTRL_Cmd(_b) HX4700_ASIC3_SD( _b, u16, Cmd ) /* */ -#define HX4700_ASIC3_SD_CTRL_Arg0(_b) HX4700_ASIC3_SD( _b, u16, Arg0 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Arg1(_b) HX4700_ASIC3_SD( _b, u16, Arg1 ) /* */ -#define HX4700_ASIC3_SD_CTRL_StopInternal(_b) HX4700_ASIC3_SD( _b, u16, StopInternal ) /* */ -#define HX4700_ASIC3_SD_CTRL_TransferSectorCount(_b) HX4700_ASIC3_SD( _b, u16, TransferSectorCount ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response0(_b) HX4700_ASIC3_SD( _b, u16, Response0 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response1(_b) HX4700_ASIC3_SD( _b, u16, Response1 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response2(_b) HX4700_ASIC3_SD( _b, u16, Response2 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response3(_b) HX4700_ASIC3_SD( _b, u16, Response3 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response4(_b) HX4700_ASIC3_SD( _b, u16, Response4 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response5(_b) HX4700_ASIC3_SD( _b, u16, Response5 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response6(_b) HX4700_ASIC3_SD( _b, u16, Response6 ) /* */ -#define HX4700_ASIC3_SD_CTRL_Response7(_b) HX4700_ASIC3_SD( _b, u16, Response7 ) /* */ -#define HX4700_ASIC3_SD_CTRL_CardStatus(_b) HX4700_ASIC3_SD( _b, u16, CardStatus ) /* */ -#define HX4700_ASIC3_SD_CTRL_BufferCtrl(_b) HX4700_ASIC3_SD( _b, u16, BufferCtrl ) /* and error status*/ -#define HX4700_ASIC3_SD_CTRL_IntMaskCard(_b) HX4700_ASIC3_SD( _b, u16, IntMask0 ) /* */ -#define HX4700_ASIC3_SD_CTRL_IntMaskBuffer(_b) HX4700_ASIC3_SD( _b, u16, IntMask1 ) /* */ -#define HX4700_ASIC3_SD_CTRL_CardClockCtrl(_b) HX4700_ASIC3_SD( _b, u16, CardClockCtrl ) /* */ -#define HX4700_ASIC3_SD_CTRL_MemCardXferDataLen(_b) HX4700_ASIC3_SD( _b, u16, MemCardXferDataLen ) /* */ -#define HX4700_ASIC3_SD_CTRL_MemCardOptionSetup(_b) HX4700_ASIC3_SD( _b, u16, MemCardOptionSetup ) /* */ -#define HX4700_ASIC3_SD_CTRL_ErrorStatus0(_b) HX4700_ASIC3_SD( _b, u16, ErrorStatus0 ) /* */ -#define HX4700_ASIC3_SD_CTRL_ErrorStatus1(_b) HX4700_ASIC3_SD( _b, u16, ErrorStatus1 ) /* */ -#define HX4700_ASIC3_SD_CTRL_DataPort(_b) HX4700_ASIC3_SD( _b, u16, DataPort ) /* */ -#define HX4700_ASIC3_SD_CTRL_TransactionCtrl(_b) HX4700_ASIC3_SD( _b, u16, TransactionCtrl ) /* */ -#define HX4700_ASIC3_SD_CTRL_SoftwareReset(_b) HX4700_ASIC3_SD( _b, u16, SoftwareReset ) /* */ - -#define _HX4700_ASIC3_SDIO_CTRL_Base 0x0900 - -#define HX4700_ASIC3_SDIO(_b, s,x) \ - (\ - (*((volatile s *) ((_b) + _HX4700_ASIC3_SDIO_CTRL_Base + (_HX4700_ASIC3_SDIO_CTRL_ ## x))))) - -#define _HX4700_ASIC3_SDIO_CTRL_Cmd 0x00 -#define _HX4700_ASIC3_SDIO_CTRL_CardPortSel 0x02 -#define _HX4700_ASIC3_SDIO_CTRL_Arg0 0x04 -#define _HX4700_ASIC3_SDIO_CTRL_Arg1 0x06 -#define _HX4700_ASIC3_SDIO_CTRL_TransferBlockCount 0x0a -#define _HX4700_ASIC3_SDIO_CTRL_Response0 0x0c -#define _HX4700_ASIC3_SDIO_CTRL_Response1 0x0e -#define _HX4700_ASIC3_SDIO_CTRL_Response2 0x10 -#define _HX4700_ASIC3_SDIO_CTRL_Response3 0x12 -#define _HX4700_ASIC3_SDIO_CTRL_Response4 0x14 -#define _HX4700_ASIC3_SDIO_CTRL_Response5 0x16 -#define _HX4700_ASIC3_SDIO_CTRL_Response6 0x18 -#define _HX4700_ASIC3_SDIO_CTRL_Response7 0x1a -#define _HX4700_ASIC3_SDIO_CTRL_CardStatus 0x1c -#define _HX4700_ASIC3_SDIO_CTRL_BufferCtrl 0x1e -#define _HX4700_ASIC3_SDIO_CTRL_IntMask0 0x20 -#define _HX4700_ASIC3_SDIO_CTRL_IntMask1 0x22 -#define _HX4700_ASIC3_SDIO_CTRL_CardXferDataLen 0x26 -#define _HX4700_ASIC3_SDIO_CTRL_CardOptionSetup 0x28 -#define _HX4700_ASIC3_SDIO_CTRL_ErrorStatus0 0x2c -#define _HX4700_ASIC3_SDIO_CTRL_ErrorStatus1 0x2e -#define _HX4700_ASIC3_SDIO_CTRL_DataPort 0x30 -#define _HX4700_ASIC3_SDIO_CTRL_TransactionCtrl 0x34 -#define _HX4700_ASIC3_SDIO_CTRL_CardIntCtrl 0x36 -#define _HX4700_ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x38 -#define _HX4700_ASIC3_SDIO_CTRL_HostInformation 0x3a -#define _HX4700_ASIC3_SDIO_CTRL_ErrorCtrl 0x3c -#define _HX4700_ASIC3_SDIO_CTRL_LEDCtrl 0x3e -#define _HX4700_ASIC3_SDIO_CTRL_SoftwareReset 0xe0 - -#define HX4700_ASIC3_SDIO_CTRL_Cmd(_b) HX4700_ASIC3_SDIO( _b, u16, Cmd ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_CardPortSel(_b) HX4700_ASIC3_SDIO( _b, u16, CardPortSel ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Arg0(_b) HX4700_ASIC3_SDIO( _b, u16, Arg0 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Arg1(_b) HX4700_ASIC3_SDIO( _b, u16, Arg1 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_TransferBlockCount(_b) HX4700_ASIC3_SDIO( _b, u16, TransferBlockCount ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response0(_b) HX4700_ASIC3_SDIO( _b, u16, Response0 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response1(_b) HX4700_ASIC3_SDIO( _b, u16, Response1 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response2(_b) HX4700_ASIC3_SDIO( _b, u16, Response2 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response3(_b) HX4700_ASIC3_SDIO( _b, u16, Response3 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response4(_b) HX4700_ASIC3_SDIO( _b, u16, Response4 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response5(_b) HX4700_ASIC3_SDIO( _b, u16, Response5 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response6(_b) HX4700_ASIC3_SDIO( _b, u16, Response6 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_Response7(_b) HX4700_ASIC3_SDIO( _b, u16, Response7 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_CardStatus(_b) HX4700_ASIC3_SDIO( _b, u16, CardStatus ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_BufferCtrl(_b) HX4700_ASIC3_SDIO( _b, u16, BufferCtrl ) /* and error status*/ -#define HX4700_ASIC3_SDIO_CTRL_IntMaskCard(_b) HX4700_ASIC3_SDIO( _b, u16, IntMask0 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_IntMaskBuffer(_b) HX4700_ASIC3_SDIO( _b, u16, IntMask1 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_CardXferDataLen(_b) HX4700_ASIC3_SDIO( _b, u16, CardXferDataLen ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_CardOptionSetup(_b) HX4700_ASIC3_SDIO( _b, u16, CardOptionSetup ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_ErrorStatus0(_b) HX4700_ASIC3_SDIO( _b, u16, ErrorStatus0 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_ErrorStatus1(_b) HX4700_ASIC3_SDIO( _b, u16, ErrorStatus1 ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_DataPort(_b) HX4700_ASIC3_SDIO( _b, u16, DataPort ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_TransactionCtrl(_b) HX4700_ASIC3_SDIO(_b)( _b, u16, TransactionCtrl ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_CardIntCtrl(_b) HX4700_ASIC3_SDIO( _b, u16, CardIntCtrl ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_ClocknWaitCtrl(_b) HX4700_ASIC3_SDIO( _b, u16, ClocknWaitCtrl ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_HostInformation(_b) HX4700_ASIC3_SDIO( _b, u16, HostInformation ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_ErrorCtrl(_b) HX4700_ASIC3_SDIO( _b, u16, ErrorCtrl ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_LEDCtrl(_b) HX4700_ASIC3_SDIO( _b, u16, LEDCtrl ) /* */ -#define HX4700_ASIC3_SDIO_CTRL_SoftwareReset(_b) HX4700_ASIC3_SDIO( _b, u16, SoftwareReset ) /* */ - - -#define HX4700_ASIC3(_b,s,x,y) \ - (*((volatile s *) (_b + _HX4700_ASIC3_ ## x ## _Base + (_HX4700_ASIC3_ ## x ## _ ## y)))) -#define _HX4700_ASIC3_CLOCK_Base 0x0500 -#define _HX4700_ASIC3_CLOCK_CDEX 0x00 -#define _HX4700_ASIC3_CLOCK_SEL 0x02 - -#define HX4700_ASIC3_CLOCK_CDEX(_b) HX4700_ASIC3( _b, u16, CLOCK, CDEX ) -#define HX4700_ASIC3_CLOCK_SEL(_b) HX4700_ASIC3( _b, u16, CLOCK, SEL ) - -#define _HX4700_ASIC3_EXTCF_Base 0x0880 - -#define _HX4700_ASIC3_EXTCF_Select 0x00 -#define _HX4700_ASIC3_EXTCF_Reset 0x02 - -#define HX4700_ASIC3_EXTCF_Select(_b) HX4700_ASIC3( _b, u16, EXTCF, Select ) -#define HX4700_ASIC3_EXTCF_Reset(_b) HX4700_ASIC3( _b, u16, EXTCF, Reset ) - - -#define _HX4700_ASIC3_SDHWCTRL_Base 0x0700 - -#define _HX4700_ASIC3_SDHWCTRL_SDConf 0x00 -#define HX4700_ASIC3_SDHWCTRL_SDConf(_b) HX4700_ASIC3( _b, u8, SDHWCTRL, SDConf ) #if 0 #ifdef CONFIG_MMC_DEBUG @@ -271,19 +72,41 @@ struct asic3_mmc_host { void *ctl_base; void *cnf_base; + void *hwctl_base; struct mmc_command *cmd; struct mmc_request *mrq; struct mmc_data *data; struct mmc_host *mmc; int irq; unsigned short clock_for_sd; - + unsigned short addr_shift; + struct device *asic3_dev; /* I/O related stuff */ struct scatterlist *sg_ptr; unsigned int sg_len; unsigned int sg_off; }; +#define sd_cnf_write(h,v,r) writew((v),(h)->cnf_base +\ + (_IPAQ_ASIC3_SD_CONFIG_ ## r>>(h)->addr_shift)) +#define sd_cnf_read(h,r) readw((h)->cnf_base +\ + (_IPAQ_ASIC3_SD_CONFIG_ ## r>>(h)->addr_shift)) + +#define sd_ctl_write(h,v,r) writew((v), (h)->ctl_base +\ + (_IPAQ_ASIC3_SD_CTRL_ ## r>>(h)->addr_shift)) +#define sd_ctl_read(h,r) readw((h)->ctl_base +\ + (_IPAQ_ASIC3_SD_CTRL_ ## r>>(h)->addr_shift)) + +#define sdio_ctl_write(h,v,r) writew((v),(h)->ctl_base +\ + ((_IPAQ_ASIC3_SDIO_CTRL_ ## r+0x200)>>(h)->addr_shift)) +#define sdio_ctl_read(h,r) readw((h)->ctl_base +\ + ((_IPAQ_ASIC3_SDIO_CTRL_ ## r+0x200)>>(h)->addr_shift)) + +#define sd_hwctl_write(h,v) writew((v),(h)->hwctl_base +\ + (_IPAQ_ASIC3_SDHWCTRL_Base>>(h)->addr_shift)) +#define sd_hwctl_read(h) readw((h)->hwctl_base +\ + (_IPAQ_ASIC3_SDHWCTRL_Base>>(h)->addr_shift)) + static void mmc_finish_request(struct asic3_mmc_host *host) { @@ -313,14 +136,13 @@ static void mmc_start_command(struct asic3_mmc_host *host, struct mmc_command *cmd) { - void *base = host->ctl_base; struct mmc_data *data = host->data; int c = cmd->opcode; /* printk("Opcode: %d, base: %p\n", cmd->opcode, base); */ if(cmd->opcode == MMC_STOP_TRANSMISSION) { - HX4700_ASIC3_SD_CTRL_StopInternal(base) = SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12; + sd_ctl_write(host, SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12, StopInternal); cmd->resp[0] = cmd->opcode; cmd->resp[1] = 0; cmd->resp[2] = 0; @@ -351,7 +173,7 @@ if(data) { c |= DATA_PRESENT; if(data->blocks > 1) { - HX4700_ASIC3_SD_CTRL_StopInternal(base) = SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12; + sd_ctl_write(host, SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12, StopInternal); c |= TRANSFER_MULTI; } if(data->flags & MMC_DATA_READ) { @@ -361,7 +183,7 @@ } /* Enable the command and data interrupts */ - HX4700_ASIC3_SD_CTRL_IntMaskCard(host->ctl_base) = ~( + sd_ctl_write(host, ~( SD_CTRL_INTMASKCARD_RESPONSE_END | SD_CTRL_INTMASKCARD_RW_END | SD_CTRL_INTMASKCARD_CARD_REMOVED_0 @@ -370,9 +192,9 @@ | SD_CTRL_INTMASKCARD_CARD_REMOVED_3 | SD_CTRL_INTMASKCARD_CARD_INSERTED_3 #endif - ); + ), IntMaskCard); - HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base) = ~( + sd_ctl_write(host, ~( SD_CTRL_INTMASKBUFFER_UNK7 | SD_CTRL_INTMASKBUFFER_CMD_BUSY #if 0 @@ -387,12 +209,12 @@ | SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE | SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS #endif - ); + ), IntMaskBuffer); /* Send the command */ - HX4700_ASIC3_SD_CTRL_Arg1(base) = cmd->arg >> 16; - HX4700_ASIC3_SD_CTRL_Arg0(base) = cmd->arg & 0xffff; - HX4700_ASIC3_SD_CTRL_Cmd(base) = c; + sd_ctl_write(host, cmd->arg >> 16, Arg1); + sd_ctl_write(host, cmd->arg & 0xffff, Arg0); + sd_ctl_write(host, c, Cmd); } /* This chip always returns (at least?) as much data as you ask for. I'm @@ -446,14 +268,14 @@ if(data->flags & MMC_DATA_READ) { while(count > 0) { /* Read two bytes from SD/MMC controller. */ - *buf = HX4700_ASIC3_SD_CTRL_DataPort(host->ctl_base); + *buf = sd_ctl_read(host, DataPort); buf++; count -= 2; } } else { while(count > 0) { /* Write two bytes to SD/MMC controller. */ - HX4700_ASIC3_SD_CTRL_DataPort(host->ctl_base) = *buf; + sd_ctl_write(host, *buf, DataPort); buf++; count -= 2; } @@ -492,13 +314,13 @@ DBG("Completed data request\n"); - HX4700_ASIC3_SD_CTRL_StopInternal(host->ctl_base) = 0; + sd_ctl_write(host, 0, StopInternal); /* Make sure read enable interrupt and write enable interrupt are disabled */ if(data->flags & MMC_DATA_READ) { - HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base) |= SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE; + sd_ctl_write(host, sd_ctl_read(host, IntMaskBuffer) | SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE, IntMaskBuffer); } else { - HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base) |= SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE; + sd_ctl_write(host, sd_ctl_read(host, IntMaskBuffer) | SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE, IntMaskBuffer); } mmc_finish_request(host); @@ -520,35 +342,35 @@ if(cmd->flags & MMC_RSP_PRESENT && cmd->flags & MMC_RSP_136) { /* R2 */ buf[12] = 0xff; - data = HX4700_ASIC3_SD_CTRL_Response0(host->ctl_base); + data = sd_ctl_read(host, Response0); buf[13] = data & 0xff; buf[14] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response1(host->ctl_base); + data = sd_ctl_read(host, Response1); buf[15] = data & 0xff; buf[8] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response2(host->ctl_base); + data = sd_ctl_read(host, Response2); buf[9] = data & 0xff; buf[10] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response3(host->ctl_base); + data = sd_ctl_read(host, Response3); buf[11] = data & 0xff; buf[4] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response4(host->ctl_base); + data = sd_ctl_read(host, Response4); buf[5] = data & 0xff; buf[6] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response5(host->ctl_base); + data = sd_ctl_read(host, Response5); buf[7] = data & 0xff; buf[0] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response6(host->ctl_base); + data = sd_ctl_read(host, Response6); buf[1] = data & 0xff; buf[2] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response7(host->ctl_base); + data = sd_ctl_read(host, Response7); buf[3] = data & 0xff; } else if(cmd->flags & MMC_RSP_PRESENT) { /* R1, R1B, R3 */ - data = HX4700_ASIC3_SD_CTRL_Response0(host->ctl_base); + data = sd_ctl_read(host, Response0); buf[0] = data & 0xff; buf[1] = data >> 8; - data = HX4700_ASIC3_SD_CTRL_Response1(host->ctl_base); + data = sd_ctl_read(host, Response1); buf[2] = data & 0xff; buf[3] = data >> 8; } @@ -568,9 +390,9 @@ | SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT ) ) { - DBG("Buffer status ERROR 0x%04x - inside check buffer\n", buffer_stat); - DBG("detail0 error status 0x%04x\n", HX4700_ASIC3_SD_CTRL_ErrorStatus0(host->ctl_base)); - DBG("detail1 error status 0x%04x\n", HX4700_ASIC3_SD_CTRL_ErrorStatus1(host->ctl_base)); + printk("Buffer status ERROR 0x%04x inside check buffer\n", buffer_stat); + printk("detail0 error status 0x%04x\n", sd_ctl_read(host,ErrorStatus0)); + printk("detail1 error status 0x%04x\n", sd_ctl_read(host,ErrorStatus1)); cmd->error = MMC_ERR_FAILED; } @@ -579,28 +401,31 @@ case SD_APP_SET_BUS_WIDTH: if(cmd->arg == SD_BUS_WIDTH_4) { host->clock_for_sd = SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD; - HX4700_ASIC3_SD_CTRL_MemCardOptionSetup(host->ctl_base) = + sd_ctl_write(host, MEM_CARD_OPTION_REQUIRED | MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(14) | MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT - | MEM_CARD_OPTION_DATA_XFR_WIDTH_4; + | MEM_CARD_OPTION_DATA_XFR_WIDTH_4, + MemCardOptionSetup); } else { host->clock_for_sd = 0; - HX4700_ASIC3_SD_CTRL_MemCardOptionSetup(host->ctl_base) = + sd_ctl_write(host, MEM_CARD_OPTION_REQUIRED | MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(14) | MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT - | MEM_CARD_OPTION_DATA_XFR_WIDTH_1; + | MEM_CARD_OPTION_DATA_XFR_WIDTH_1, + MemCardOptionSetup); } break; case MMC_SELECT_CARD: if((cmd->arg >> 16) == 0) { /* We have been deselected. */ - HX4700_ASIC3_SD_CTRL_MemCardOptionSetup(host->ctl_base) = + sd_ctl_write(host, MEM_CARD_OPTION_REQUIRED | MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(14) | MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT - | MEM_CARD_OPTION_DATA_XFR_WIDTH_1; + | MEM_CARD_OPTION_DATA_XFR_WIDTH_1, + MemCardOptionSetup); } } } @@ -612,12 +437,12 @@ if(host->data && (cmd->error == MMC_ERR_NONE)){ if(host->data->flags & MMC_DATA_READ) { /* Enable the read enable interrupt */ - HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base) &= - ~SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE; + sd_ctl_write(host, (sd_ctl_read(host, IntMaskBuffer) & + ~SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE), IntMaskBuffer); } else { /* Enable the write enable interrupt */ - HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base) &= - ~SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE; + sd_ctl_write(host, (sd_ctl_read(host, IntMaskBuffer) & + ~SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE), IntMaskBuffer); } } else { /* There's no data, or we encountered an error, so finish now. */ @@ -646,18 +471,18 @@ host = irq_desc; /* asic3 bstatus has errors */ - bstatus = HX4700_ASIC3_SD_CTRL_BufferCtrl(host->ctl_base); - bmask = HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base); - cstatus = HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base); - cmask = HX4700_ASIC3_SD_CTRL_IntMaskCard(host->ctl_base); + bstatus = sd_ctl_read(host, BufferCtrl); + bmask = sd_ctl_read(host, IntMaskBuffer); + cstatus = sd_ctl_read(host, CardStatus); + cmask = sd_ctl_read(host, IntMaskCard); breg = bstatus & ~bmask & ~DONT_CARE_BUFFER_BITS; creg = cstatus & ~cmask & ~DONT_CARE_CARD_BITS; if (!breg && !creg) { /* This occurs sometimes for no known reason. It doesn't hurt * anything, so I don't print it. */ - HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base) &= ~breg; - HX4700_ASIC3_SD_CTRL_IntMaskCard(host->ctl_base) &= ~creg; + sd_ctl_write(host, (sd_ctl_read(host, IntMaskBuffer) & ~breg), IntMaskBuffer); + sd_ctl_write(host, (sd_ctl_read(host, IntMaskCard) & ~creg), IntMaskCard); goto out; } @@ -672,8 +497,8 @@ */ /* XXX Asic3 has _3 versions of these status bits, too, for a second slot, perhaps? */ if (creg & (SD_CTRL_CARDSTATUS_CARD_INSERTED_0 | SD_CTRL_CARDSTATUS_CARD_REMOVED_0)) { - HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base) &= - ~(SD_CTRL_CARDSTATUS_CARD_REMOVED_0 | SD_CTRL_CARDSTATUS_CARD_INSERTED_0); + sd_ctl_write(host, sd_ctl_read(host, CardStatus) & + ~(SD_CTRL_CARDSTATUS_CARD_REMOVED_0 | SD_CTRL_CARDSTATUS_CARD_INSERTED_0), CardStatus); if(creg & SD_CTRL_CARDSTATUS_CARD_INSERTED_0) { hwinit2_irqsafe(host); } @@ -682,38 +507,38 @@ /* Command completion */ if (creg & SD_CTRL_CARDSTATUS_RESPONSE_END) { - HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base) &= - ~(SD_CTRL_CARDSTATUS_RESPONSE_END); + sd_ctl_write(host, sd_ctl_read(host, CardStatus) & + ~(SD_CTRL_CARDSTATUS_RESPONSE_END), CardStatus); mmc_cmd_irq(host, bstatus); } /* Data transfer */ if (breg & (SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE | SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE)) { - HX4700_ASIC3_SD_CTRL_BufferCtrl(host->ctl_base) &= - ~(SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE | SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE); + sd_ctl_write(host, sd_ctl_read(host, BufferCtrl) & + ~(SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE | SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE), BufferCtrl); /* mmc_data_transfer(host); */ tasklet_schedule(&mmc_data_read_tasklet); } /* Data transfer completion */ if (creg & SD_CTRL_CARDSTATUS_RW_END) { - HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base) &= ~(SD_CTRL_CARDSTATUS_RW_END); + sd_ctl_write(host, sd_ctl_read(host, CardStatus) & ~(SD_CTRL_CARDSTATUS_RW_END), CardStatus); mmc_data_end_irq(host); } /* Check status - keep going until we've handled it all */ - bstatus = HX4700_ASIC3_SD_CTRL_BufferCtrl(host->ctl_base); - bmask = HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base); - cstatus = HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base); - cmask = HX4700_ASIC3_SD_CTRL_IntMaskCard(host->ctl_base); + bstatus = sd_ctl_read(host, BufferCtrl); + bmask = sd_ctl_read(host, IntMaskBuffer); + cstatus = sd_ctl_read(host, CardStatus); + cmask = sd_ctl_read(host, IntMaskCard); breg = bstatus & ~bmask & ~DONT_CARE_BUFFER_BITS; creg = cstatus & ~cmask & ~DONT_CARE_CARD_BITS; } out: /* Ensure all interrupt sources are cleared */ - HX4700_ASIC3_SD_CTRL_BufferCtrl(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base) = 0; + sd_ctl_write(host, 0, BufferCtrl); + sd_ctl_write(host, 0, CardStatus); return IRQ_HANDLED; } @@ -729,8 +554,8 @@ host->data = data; /* Set transfer length and blocksize */ - HX4700_ASIC3_SD_CTRL_TransferSectorCount(host->ctl_base) = data->blocks; - HX4700_ASIC3_SD_CTRL_MemCardXferDataLen(host->ctl_base) = 1 << data->blksz_bits; + sd_ctl_write(host, data->blocks, TransferSectorCount); + sd_ctl_write(host, 1 << data->blksz_bits, MemCardXferDataLen); } /* Process requests from the MMC layer */ @@ -780,29 +605,29 @@ if(ios->clock >= 24000000 / 2) clk >>= 1; if(ios->clock >= 24000000 / 1) clk >>= 1; if(clk == 0) { /* For fastest speed we disable the divider. */ - HX4700_ASIC3_SD_CONFIG_ClockMode(host->ctl_base) = 0; + sd_cnf_write(host, 0, ClockMode); } else { - HX4700_ASIC3_SD_CONFIG_ClockMode(host->ctl_base) = 1; + sd_cnf_write(host, 1, ClockMode); } - HX4700_ASIC3_SD_CTRL_CardClockCtrl(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_CardClockCtrl(host->ctl_base) = + sd_ctl_write(host, 0, CardClockCtrl); + sd_ctl_write(host, host->clock_for_sd | SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK - | clk; + | clk, CardClockCtrl); msleep(10); } else { - HX4700_ASIC3_SD_CTRL_CardClockCtrl(host->ctl_base) = 0; + sd_ctl_write(host, 0, CardClockCtrl); } switch (ios->power_mode) { case MMC_POWER_OFF: - HX4700_ASIC3_SD_CONFIG_SDHC_Power1(host->ctl_base) = 0; + sd_cnf_write(host, 0, SDHC_Power1); msleep(1); break; case MMC_POWER_UP: break; case MMC_POWER_ON: - HX4700_ASIC3_SD_CONFIG_SDHC_Power1(host->ctl_base) = SD_CONFIG_POWER1_PC_33V; + sd_cnf_write(host, SD_CONFIG_POWER1_PC_33V, SDHC_Power1); msleep(20); break; } @@ -814,7 +639,7 @@ struct asic3_mmc_host *host = mmc_priv(mmc); /* WRITE_PROTECT is active low */ - return (HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base) & SD_CTRL_CARDSTATUS_WRITE_PROTECT)?0:1; + return (sd_ctl_read(host, CardStatus) & SD_CTRL_CARDSTATUS_WRITE_PROTECT)?0:1; } static struct mmc_host_ops mmc_ops = { @@ -826,44 +651,44 @@ static void hwinit2_irqsafe(struct asic3_mmc_host *host) { - HX4700_ASIC3_SD_CONFIG_Addr1(host->ctl_base) = 0x0000; - HX4700_ASIC3_SD_CONFIG_Addr0(host->ctl_base) = 0x0800; + sd_cnf_write(host, 0, Addr1); + sd_cnf_write(host, 0x0800, Addr0); - HX4700_ASIC3_SD_CONFIG_ClkStop(host->ctl_base) = SD_CONFIG_CLKSTOP_ENABLE_ALL; - HX4700_ASIC3_SD_CONFIG_SDHC_CardDetect(host->ctl_base) = 2; - HX4700_ASIC3_SD_CONFIG_Command(host->ctl_base) = SD_CONFIG_COMMAND_MAE; + sd_cnf_write(host, SD_CONFIG_CLK_ENABLE_ALL, ClkStop); + sd_cnf_write(host, 2, SDHC_CardDetect); + sd_cnf_write(host, SD_CONFIG_COMMAND_MAE, Command); - HX4700_ASIC3_SD_CTRL_SoftwareReset(host->ctl_base) = 0; /* reset on */ + sd_ctl_write(host, 0, SoftwareReset); /* reset on */ mdelay(2); - HX4700_ASIC3_SD_CTRL_SoftwareReset(host->ctl_base) = 1; /* reset off */ + sd_ctl_write(host, 1, SoftwareReset); /* reset off */ mdelay(2); - HX4700_ASIC3_SD_CTRL_MemCardOptionSetup(host->ctl_base) = + sd_ctl_write(host, MEM_CARD_OPTION_REQUIRED | MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(14) | MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT | MEM_CARD_OPTION_DATA_XFR_WIDTH_1 - ; + , MemCardOptionSetup); host->clock_for_sd = 0; - HX4700_ASIC3_SD_CTRL_CardClockCtrl(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_CardStatus(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_BufferCtrl(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_ErrorStatus0(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_ErrorStatus1(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_StopInternal(host->ctl_base) = 0; + sd_ctl_write(host, 0, CardClockCtrl); + sd_ctl_write(host, 0, CardStatus); + sd_ctl_write(host, 0, BufferCtrl); + sd_ctl_write(host, 0, ErrorStatus0); + sd_ctl_write(host, 0, ErrorStatus1); + sd_ctl_write(host, 0, StopInternal); - HX4700_ASIC3_SDIO_CTRL_ClocknWaitCtrl(host->ctl_base) = 0x100; + sdio_ctl_write(host, 0x100, ClocknWaitCtrl); /* *((unsigned short *)(((char *)host->ctl_base) + 0x938)) = 0x100; */ - HX4700_ASIC3_SD_CONFIG_ClockMode(host->ctl_base) = 0; - HX4700_ASIC3_SD_CTRL_CardClockCtrl(host->ctl_base) = 0; + sd_cnf_write(host, 0, ClockMode); + sd_ctl_write(host, 0, CardClockCtrl); mdelay(1); - HX4700_ASIC3_SD_CTRL_IntMaskCard(host->ctl_base) = ~( + sd_ctl_write(host, ~( SD_CTRL_INTMASKCARD_RESPONSE_END | SD_CTRL_INTMASKCARD_RW_END | SD_CTRL_INTMASKCARD_CARD_REMOVED_0 @@ -872,9 +697,9 @@ | SD_CTRL_INTMASKCARD_CARD_REMOVED_3 | SD_CTRL_INTMASKCARD_CARD_INSERTED_3 #endif - ) + ), IntMaskCard) ; /* check */ - HX4700_ASIC3_SD_CTRL_IntMaskBuffer(host->ctl_base) = 0xffff; /* IRQs off */ + sd_ctl_write(host, 0xffff, IntMaskBuffer); /* IRQs off */ /* * HX4700_ASIC3_SD_CTRL_TransactionCtrl(host->ctl_base) = SD_CTRL_TRANSACTIONCONTROL_SET; @@ -882,24 +707,24 @@ */ /* HX4700_ASIC3_SD_CTRL_TransactionCtrl(host->ctl_base) = 0x1000; */ - - HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base) |= ASIC3_SDHWCTRL_SDPWR; /* turn on power at controller(?) */ + + sd_hwctl_write(host, sd_hwctl_read(host) | ASIC3_SDHWCTRL_SDPWR); } static void hwinit(struct asic3_mmc_host *host, struct device *dev) { - HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base) |= ASIC3_SDHWCTRL_LEVCD; - HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base) |= ASIC3_SDHWCTRL_LEVWP; - HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base) &= 0xfffe; - HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base) &= 0xfffb; + sd_hwctl_write(host, sd_hwctl_read(host) | ASIC3_SDHWCTRL_LEVCD); + sd_hwctl_write(host, sd_hwctl_read(host) | ASIC3_SDHWCTRL_LEVWP); + sd_hwctl_write(host, sd_hwctl_read(host) & 0xfffe); + sd_hwctl_write(host, sd_hwctl_read(host) & 0xfffb); #if 0 HX4700_ASIC3_CLOCK_CDEX(host->cnf_base) |= 0x4000; HX4700_ASIC3_CLOCK_CDEX(host->cnf_base) |= 0x2000; #endif - asic3_set_clock_cdex (&hx4700_asic3.dev, + asic3_set_clock_cdex(host->asic3_dev, CLOCK_CDEX_EX1 | CLOCK_CDEX_EX0, CLOCK_CDEX_EX1 | CLOCK_CDEX_EX0); msleep(1); @@ -907,7 +732,7 @@ HX4700_ASIC3_CLOCK_SEL(host->cnf_base) |= 1; HX4700_ASIC3_CLOCK_SEL(host->cnf_base) &= 0xfffd; #endif - asic3_set_clock_sel (&hx4700_asic3.dev, + asic3_set_clock_sel (host->asic3_dev, CLOCK_SEL_SD_HCLK_SEL | CLOCK_SEL_SD_BCLK_SEL, CLOCK_SEL_SD_HCLK_SEL | 0); @@ -915,7 +740,7 @@ HX4700_ASIC3_CLOCK_CDEX(host->cnf_base) |= 0x200; HX4700_ASIC3_CLOCK_CDEX(host->cnf_base) |= 0x400; #endif - asic3_set_clock_cdex (&hx4700_asic3.dev, + asic3_set_clock_cdex (host->asic3_dev, CLOCK_CDEX_SD_HOST | CLOCK_CDEX_SD_BUS, CLOCK_CDEX_SD_HOST | CLOCK_CDEX_SD_BUS); msleep(1); @@ -927,7 +752,7 @@ #if 0 HX4700_ASIC3_EXTCF_Select(host->cnf_base) |= 0x4000; #endif - asic3_set_extcf_select(&hx4700_asic3.dev, ASIC3_EXTCF_SD_MEM_ENABLE, ASIC3_EXTCF_SD_MEM_ENABLE); + asic3_set_extcf_select(host->asic3_dev, ASIC3_EXTCF_SD_MEM_ENABLE, ASIC3_EXTCF_SD_MEM_ENABLE); /* Long Delay */ /* msleep(500); */ @@ -941,21 +766,21 @@ { struct mmc_host *mmc = dev_get_drvdata(dev); struct asic3_mmc_host *host = mmc_priv(mmc); - unsigned long adat; /* disable the card insert / remove interrupt while sleeping */ - HX4700_ASIC3_SD_CTRL_IntMaskCard(host->ctl_base) = ~( + sd_ctl_write(host, ~( SD_CTRL_INTMASKCARD_RESPONSE_END - | SD_CTRL_INTMASKCARD_RW_END); + | SD_CTRL_INTMASKCARD_RW_END), IntMaskCard); /* disable clock */ - HX4700_ASIC3_SD_CTRL_CardClockCtrl(host->ctl_base) = 0; - HX4700_ASIC3_SD_CONFIG_ClkStop(host->ctl_base) = 0; + sd_ctl_write(host, 0, CardClockCtrl); + sd_cnf_write(host, 0, ClkStop); + /* power down */ - HX4700_ASIC3_SD_CONFIG_SDHC_Power1(host->ctl_base) = 0; + sd_cnf_write(host, 0, SDHC_Power1); - asic3_set_clock_cdex (&hx4700_asic3.dev, + asic3_set_clock_cdex (host->asic3_dev, CLOCK_CDEX_SD_HOST | CLOCK_CDEX_SD_BUS, 0); #if 0 /* disable core clock */ @@ -964,9 +789,7 @@ #endif /* Put in suspend mode */ - adat = HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base); - adat |= ASIC3_SDHWCTRL_SUSPEND; - HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base) = adat; + sd_hwctl_write(host, sd_hwctl_read(host) | ASIC3_SDHWCTRL_SUSPEND); return 0; } @@ -995,19 +818,16 @@ { struct mmc_host *mmc = dev_get_drvdata(dev); struct asic3_mmc_host *host = mmc_priv(mmc); - unsigned long adat; - adat = HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base); - adat &= ~ASIC3_SDHWCTRL_SUSPEND; - HX4700_ASIC3_SDHWCTRL_SDConf(host->cnf_base) = adat; + sd_hwctl_write(host, sd_hwctl_read(host) & ~ASIC3_SDHWCTRL_SUSPEND); hwinit(host, dev); /* re-enable card remove / insert interrupt */ - HX4700_ASIC3_SD_CTRL_IntMaskCard(host->ctl_base) = ~( + sd_ctl_write(host, ~( SD_CTRL_INTMASKCARD_RESPONSE_END | SD_CTRL_INTMASKCARD_RW_END | SD_CTRL_INTMASKCARD_CARD_REMOVED_0 - | SD_CTRL_INTMASKCARD_CARD_INSERTED_0 ); + | SD_CTRL_INTMASKCARD_CARD_INSERTED_0 ), IntMaskCard); /* See note in mmc_resume_task_handler() about why there is a delay here. */ schedule_delayed_work( &mmc_resume_task, 2 * HZ ); @@ -1020,6 +840,9 @@ { struct mmc_host *mmc; struct asic3_mmc_host *host; + struct resource *cnf, *ctl; + struct platform_device *pdev = to_platform_device(dev); + struct asic3_platform_data *pdata; int retval = 0; host = 0; @@ -1035,21 +858,31 @@ dev_set_drvdata(dev, mmc); host->cnf_base = host->ctl_base = 0; + cnf = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + host->asic3_dev = dev->platform_data; + pdata = host->asic3_dev->platform_data; + host->addr_shift = (pdata && pdata->bus_shift) ? 1 : 0; + host->clock_for_sd = 0; tasklet_init(&mmc_data_read_tasklet, mmc_data_transfer, (unsigned long)host); mmc_resume_task.data = mmc; - host->cnf_base = ioremap_nocache(0x0c000000, 0x2000); + host->cnf_base = ioremap(cnf->start, cnf->end - cnf->start + 1); if(!host->cnf_base){ goto exceptional_return; } - host->ctl_base = host->ctl_base = ioremap(0x0e000000, 0x2000); + host->ctl_base = ioremap(ctl->start, ctl->end - ctl->start + 1); if(!host->ctl_base){ goto exceptional_return; } + host->hwctl_base = ioremap_nocache(0x0c000000, 0x2000); // XXX ASIC3 base + //host->hwctl_base = asic3_address(host->asic3_dev, 0); + mmc->ops = &mmc_ops; mmc->caps = MMC_CAP_4_BIT_DATA; mmc->f_min = 46875; /* ARIC: not sure what these should be */ @@ -1059,7 +892,7 @@ hwinit(host, dev); - host->irq = HX4700_IRQ(ASIC3_SDIO_INT_N); + host->irq = platform_get_irq(pdev, 0); retval = request_irq(host->irq, mmc_irq, 0 /* SA_INTERRUPT */, DRIVER_NAME, host); if(retval) {