File: headers\targa.h
1 /* targa.h */
2
3
4 #ifndef TARGA_H
5 #define TARGA_H
6
7
8 extern unsigned int _dataseg_xx;
9
10 /****************************************************************/
11
12 #ifdef __TURBOC__
13 # define PEEK(a,b,c,d) movedata( b, a, _DS, c, d)
14 # define POKE(a,b,c,d) movedata( _DS, c, b, a, d )
15 # define OUTPORTB outportb
16 # define INPORTB inportb
17 # define OUTPORTW outport
18 # define INPORTW inport 19 #else
20 # define PEEK(a,b,c,d) movedata( b, a, _dataseg_xx, c, d)
21 # define POKE(a,b,c,d) movedata( _dataseg_xx, c, b, a, d )
22 # define OUTPORTB outp
23 # define INPORTB inp
24 # define OUTPORTW outpw
25 # define INPORTW inpw
26 #endif
27
28 #define FALSE 0
29 #ifdef TRUE
30 #undef TRUE
31 #endif
32 #define TRUE 1
33
34 /****************************************************************/
35
36 #define TSEG 0xA000
37 #define TIOBASE 0x220
38
39
40 /****************************************************************/
41
42
43 #define TYPE_8 8
44 #define TYPE_16 16
45 #define TYPE_24 24
46 #define TYPE_32 32
47 #define TYPE_M8 -8
48
49 /*
50 * TARGA: 400 to 482 rows x 512 pixels/row X 16 bits/pixel
51 */
52
53 #define XMIN 0
54 #define YMIN 0
55 #define XMAX 512 /* maximum X value */
56 #define YMAX 512 /* maximum Y value */
57 #define XRES 512 /* X resolution */
58 #define YRES 512 /* Y Resolution */
59 #define YVISMAX (2*targa.LinesPerField) /* Maximum visible Y coordinate */
60 #define YVISMIN 0 /* Minimum visible Y coordiate */
61 #define DEF_ROWS 400 /* Default number of rows */
62
63 #define IOBASE targa.iobase /* io base location of graphics registers */
64 #define MEMSEG targa.memloc /* use the variable so we can use */
65 #define SCNSEG targa.memloc /* the one defined in TARGA */
66 #define SRCBANK (targa.memloc+0x0800) /* use high-bank as source bank */
67 #define DESTBANK targa.memloc /* use lo-bank as destination bank */
68
69 /* Output register definitions */
70 #define MODEREG (IOBASE+0xC00) /* Mode Register address */
71 #define MASKREG (IOBASE+0x800) /* Mask Registers */
72 #define UNDERREG (IOBASE+0x800) /* Underscan register */
73 #define OVERREG (IOBASE+0x802) /* overscan register */
74 #define DESTREG (IOBASE+0x802) /* Address of Page Select Lower Register */
75 #define SRCREG (IOBASE+0x803) /* Address of Page Select Upper Register */
76 #define VCRCON (IOBASE+0x400) /* Address of Contrast/VidSrc Register */
77 #define BLNDREG VCRCON
78 #define SATHUE (IOBASE+0x402) /* Satuation/Hue Register address */
79 #define DRREG (IOBASE+0x401) /* ADDRESS OF Controller Write Register */
80 #define VERTPAN (IOBASE+0x403) /* Address of Vertical Pan Register */
81 #define BORDER (IOBASE) /* Address of Page Select Lower Register */
82
83 /* Input register definitions */
84 #define VIDEOSTATUS (IOBASE+0xC02) /* Video Status Register */
85 #define RASTERREG (IOBASE+0xC00) /* Raster counter register */
86
87 /* Default register values */
88 #define DEF_MODE 1 /* Default mode register value */
89 /* Memory selected, 512x512, 1x */
90 /* Display mode */
91 #define DEF_MASK 0 /* default memory mask */
92 #define DEF_SATURATION 0x4 /* default saturation value */
93 #define DEF_HUE 0x10 /* default hue value */
94 #define DEF_CONTRAST 0x10 /* default contrast value */
95 #define DEF_VIDSRC 0 /* default video source value - Composite */
96 #define DEF_VERTPAN 56 /* assumes 400-line output */
97 #define DEF_BORDER 0 /* default border color */
98
99
100 /* MASK AND SHIFT VALUE FOR REGISTERS CONTAINING SUBFIELDS */
101 /*
102 * ******************************************************
103 * MODE REGISTERS
104 * ******************************************************
105 */
106 #define MSK_MSEL 0xfffC /* memory select bits */
107 #define SHF_MSEL 0x0000
108 #define MSEL 1
109
110 #define MSK_IBIT 0xfffb /* Interlace bit */
111 #define SHF_IBIT 2
112
113 #define MSK_RES 0xFFC7 /* disp. resolution and screen select bits */
114 #define SHF_RES 3
115 #define S0_512X512_0 0 /* 512x512 resolution screen */
116 #define S1_512X512_1 1
117 #define S2_512X256_0 2 /* 512x256 resolution screen 0 */
118 #define S3_512X256_1 3 /* 512x256 resolution screen 1 */
119 #define S4_256X256_0 4 /* 256x256 resolution screen 0 */
120 #define S5_256X256_1 5 /* .... */
121 #define S6_256X256_2 6
122 #define S7_256X256_3 7
123
124 #define MSK_REGWRITE 0xFFBF /* mask for display register write */
125 #define SHF_REGWRITE 6
126 #define REGINDEX 0 /* to write an index value */
127 #define REGVALUE 1 /* to write a value */
128
129 #define MSK_BIT9 0xFF7F /* maks for high-order bit of DR's */
130 #define SHF_BIT9 7
131
132 #define MSK_TAPBITS 0xFCFF /* mask for setting the tap bits */
133 #define SHF_TAPBITS 8
134
135 #define MSK_ZOOM 0xF3FF /* Mask for zoom factor */
136 #define SHF_ZOOM 10
137
138 #define MSK_DISPLAY 0xCFFF /* Mask for display mode */
139 #define SHF_DISPLAY 12
140 #define MEMORY_MODE 0
141 #define LIVE_FIXED 1
142 #define OVERLAY_MODE 2
143 #define LIVE_LIVE 3
144 #define DEF_DISPLAY 0
145
146 #define MSK_CAPTURE 0xBFFF /* Mask for capture bit */
147 #define SHF_CAPTURE 14
148
149 #define MSK_GENLOCK 0x7FFF /* MASK FOR GENLOCK */
150 #define SHF_GENLOCK 15
151 #define DEF_GENLOCK 0
152
153 /* Video status input register */
154 #define FIELDBIT 0x0001
155 #define VIDEOLOSS 0x0002
156
157 /* VIDEO SOURCE/CONTROL REGISTER */
158 #define MSK_CONTRAST 0xFFC1
159 #define SHF_CONTRAST 1
160 #define MAX_CONTRAST 0x1f
161
162 #define MSK_RGBORCV 0xBF
163 #define SHF_RGBORCV 6
164 #define RGB 1
165 #define CV 0
166
167 #define MSK_VCRORCAMERA 0x7F
168 #define SHF_VCRORCAMERA 7
169 #define VCR 1
170 #define CAMERA 0
171
172 /* HUE/SATUATION REGISTER */
173 #define MSK_HUE 0xE0
174 #define SHF_HUE 0
175 #define MAX_HUE 0x1f
176
177 #define MSK_SATURATION 0x1F
178 #define SHF_SATURATION 5
179 #define MAX_SATURATION 0x07
180
181
182 /*
183 * *********************************************
184 * Display register settings
185 * *********************************************
186 *
187 * Screen Positioning Registers:
188 * DR 0-3
189 */
190 #define LEFTBORDER 0
191 #define DEF_LEFT 85
192 #define MIN_LEFT 75
193 #define MAX_LEFT 95
194 #define RIGHTBORDER 1
195 #define DEF_RIGHT (DEF_LEFT+256)
196 #define TOPBORDER 2
197 #define DEF_TOP 40
198 #define MIN_TOP 20
199 #define BOTTOMBORDER 3
200 #define DEF_BOTTOM (DEFTOP+DEFROWS/2)
201 #define MAX_BOTTOM 261
202
203 /* REgisters which track 0-3 */
204 #define DR8 8
205 #define PRESHIFT DR8
206 #define EQU_DR8 DR0
207 #define DR9 9
208 #define EQU_DR9 DR1
209 #define DR10 10
210 #define EQU_DR10 DR2
211 #define DR11 11
212 #define EQU_DR11 DR3
213
214 /* REQUIRED REGISTERS */
215 #define DR4 4
216 #define DEF_DR4 352
217 #define DR5 5
218 #define DEF_DR5 1
219 #define DR6 6
220 #define DEF_DR6 0
221 #define DR7 7
222 #define DEF_DR7 511
223 #define DR12 12
224 #define DEF_DR12 20
225 #define DR13 13
226 #define DEF_DR13 22
227 #define DR14 14
228 #define DEF_DR14 0
229 #define DR15 15
230 #define DEF_DR15 511
231 #define DR16 16
232 #define DEF_DR16 0
233 #define DR17 17
234 #define DEF_DR17 0
235 #define DR18 18
236 #define DEF_DR18 0
237 #define DR19 19
238 #define DEF_DR19 4
239
240 /* interlace mode register & parameters */
241 #define DR20 20
242 #define INTREG 0x14
243 #define DEF_INT 0 /* default to interlace mode 0 */
244 #define MSK_INTERLACE 0x0003
245
246 /**************************************************************/
247
248
249 typedef struct {
250 /* Board Configuration */
251 int memloc; /* memory segment */
252 int iobase; /* IOBASE segment */
253 int BytesPerPixel; /* number of words per pixel */
254 int RowsPerBank; /* number of row per 64K bank */
255 int MaxBanks; /* maximum bank id */
256 int AddressShift; /* number of bits to shift address */
257
258 /* Control registers */
259 int mode; /* mode register */
260 int Mask; /* mask register */
261 int PageMode; /* current page mode (screen res. and page) */
262 unsigned PageLower; /* Lower Page Select register */
263 unsigned PageUpper; /* upper Page select register */
264 int VCRCon; /* VCRContract register */
265 int SatHue; /* Hue and Saturation register */
266 long BorderColor; /* Border color register */
267 int VertShift; /* Vertical Pan Register */
268 int PanXOrig, PanYOrig; /* x,y pan origin */
269
270 /* TARGA-SET PARAMETERS */
271 int boardType; /* See TYPE_XX IN THIS FILE */
272 /* FOR DEFINITION OF Board Types */
273 int xOffset; /* X-offset */
274 int yOffset; /* Y-Offset */
275 int LinesPerField; /* maximum visible row count */
276 int InterlaceMode; /* desired interlace mode */
277 int AlwaysGenLock; /* Genlock always on or not */
278 int Contrast; /* Desired Contrast */
279 int Hue; /* Desired Hue */
280 int Saturation; /* Desired Satuation */
281 int RGBorCV; /* CV or RGB Input */
282 int VCRorCamera; /* VCR or Camera */
283 int ovrscnAvail, ovrscnOn; /* ovrscnAvail 1 if Overscan installed */
284 /* ovrscnOn 1 if overscan is stretching */
285 /* Display Registers */
286 int DisplayRegister[22];
287
288 } TARStruct;
289
290
291 /****************************************************************/
292 /* Data Definitions */
293
294 #ifdef TARGA_DATA
295 # define _x_
296 # define eq( val ) =val
300 #endif
301
302 _x_ int tseg eq( TSEG );
303 _x_ int tiobase eq( TIOBASE );
304
305 _x_ TARStruct targa;
306
307 #undef _x_
308 #undef eq
309
310 #endif
311
312