Source: Mapping the Atari, by Ian Chadwick
D400 (W): DMACTL D401 (W): CHACTL D402, D403 (W): DLISTL, DLISTH D404 (W): HSCROL D405 (W): VSCROL D406: (unused) D407 (W): PMBASE D408: (unused) D409 (W): CHBASE D40A (W): WSYNC D40B (R): VCOUNT D40C (R): PENH D40D (R): PENV D40E (W): NMIEN D40F (W): NMIRES D40F (R): NMIST
|unused||DL DMA||PM Rez||P DMA||M DMA||Playfield Width|
DL DMA: Enables ANTIC to access the playfield display list and screen data in memory. If this bit is off, there can be no playfield.
PM Rez: If set, player and missile data are updated every scan line. If clear, player and missile data are updated every two scan lines. This affects both the size and page alignment of the player/missile data table.
P DMA: Enables ANTIC to access the player/missile data table in memory and send player data to CTIA/GTIA.
M DMA: Enables ANTIC to access the player/missile data table in memory and send missile data to CTIA/GTIA.
Playfield Width: Sets the size of the playfield:
0: no playfield
1: narrow playfield (128 color clocks)
2: normal playfield (160 color clocks)
3: wide playfield (192 color clocks)
Notes: If display list DMA is on but player and missle DMA are both off, random player and missile data will be sent to CTIA/GTIA on the first scan line of each display mode line. If either player or missile DMA is on but not the other, random missile or player data (respectively) will be sent to CTIA/GTIA on every scan line. If all three DMA controls are off, ANTIC will not send and player or missile data to CTIA/GTIA. Note that CTIA/GTIA is not obligated to read any of this data (see GRACTL.)
(At least on my television,) the useable screen area is 172 color clocks, starting from clock #44 and ending at clock #215. On a wide text playfield, the first three columns and the last two are off the edge of the screen.
|unused||Upside- Down||Inverse Video||Opaque|
This register controls the display of characters that have bit 7 set (inverted characters by default).
Sets the initial address of the display list data. Note that a display list cannot cross a 1K boundary unless you use a JMP instruction. The internal display list pointer will change during the course of a screen frame, according to the display list data. The operating system normally rewrites this during every vblank period from the shadow registers at $230 and $231.
Number of color clocks to scroll a mode line horizontally. Only affects lines that have the HScroll bit set. Only the 4 low-order bits are used, which means the horizontal scroll is limited to 15 color clocks. The largest mode lines (8 and 9) only use 16 color clocks per byte of pixel data. The mode line is scrolled to the right; i.e., a line that would read:
if HSCROL were 0, would change to:
when HSCROL is changed to 4. To put it another way: if HSCROL is set to F, the first pixel shown will be the second color clock from the normal start of the screen data; if HSCROL is set to 0, the first pixel shown will be the 17th color clock from the normal start of the screen data.
Number of scan lines to scroll a mode line vertically. Only affects lines that have the VScroll bit set. Only the 4 low-order bits are used, which means the vertical scroll is limited to 15 scan lines. The largest mode lines (text modes 5 and 7) have only 16 scan lines in them anyway. The mode line is scrolled up; i.e., if VSCROL is 4, a text line would show the bottom half of the current line followed by the top half of the next line.
High-order byte of the base address of player/missile data. Note that the address must be on a 1K boundary for double line players, and on a 2K boundary for single line players. The memory layout for player/missle data is as follows:
|double line||single line|
|+ 512||Player 0|
|+ 640||Player 1|
|+ 768||Player 2||M3||M2||M1||M0|
|+ 896||Player 3|
|+ 1024||Player 0|
|+ 1280||Player 1|
|+ 1536||Player 2|
|+ 1792||Player 3|
High-order byte of the base address of character font data. For ANTIC modes 2-5, only the top 6 bits are used. For ANTIC modes 6 and 7, only the top 7 bits are used. This means that a full 128-character font set must begin on a 1K boundary, and a 64-character font set must begin on a ½K boundary.
Within the font set, characters are not arranged in ATASCII order, but by screen byte. The discrepancy between screen byte value and ATASCII value is enforced solely by the OS; another OS could easily be written that would make screen data match ATASCII values and just reorganize the font data. However, that method would only work for the 128-character modes. The relationship between ATASCII and screen data is shown in the following table:
|00 - 1F
(Atari text graphics)
|40 - 5F|
|20 - 3F
(numbers and punctuation)
|00 - 1F|
|40 - 5F
|20 - 3F|
|60 - 7F
|60 - 7F|
In ANTIC modes 6 and 7, which only use the lower 6 bits of the screen byte for the font index, the above translation results in a choice between uppercase letters and punctuation, or lowercase letters and text graphics.
Notes: CHBASE may be changed on the fly; i.e., if it is changed in the middle of a text line, the previous part of that line will be in the old font and the remainder of that line will be shown in the new font. Additionally, the data in a single font may also be changed on the fly. On the other hand, screen byte data is only read during the first scan line of a text mode line, and it is cached for use during the remaining scan lines.
A write to this register (but not a read) causes ANTIC to halt the CPU until 4.47µs before the next scan line. (That's 7 machine cycles, or 14 color clocks.)
Returns half the value of the vertical line counter. The range of values is from 0 through 130.
Holds the value the horizontal color clock counter held at the time the light pen was triggered.
Holds half the value the vertical line counter held at the time the light pen was triggered.
DLI: Enables display list interrupts.
VBI: Enables vertical blank interrupts.
Reset: Enables RESET button interrupts. Note: this bit really has no effect on the CPU. Pressing RESET will still reset the CPU, as long as it's not in the middle of a JAM instruction.
A write to this register clears the NMIST register.
Returns the NMI interrupt status. The bits are set if the corresponding type of interrupt is pending; otherwise they are clear.